CXL has seen a massive surge recently, and Marvell announced its second-generation Structera X CXL memory expanders, adding CXL 3.2 support, PCIe Gen6 connectivity, and increasing memory channels from four to six. For hyperscalers running DDR4 and lower-speed DDR5 reclamation projects, that means the DDR4 version can support up to 18 DDR4 RDIMMs.
Patrick gave us the decoder for the models:
- CXL 3 support is indicated by the first digit 3, just as the 2 in last year’s 2404 and 2504 marked CXL 2.0.
- 5 or 4, is the DDR generation
- The trailing two digits are the memory channel count.
Structera X 3406 is therefore a CXL 3 DDR4 part with six channels, while the 3506 is the CXL 3 DDR5 part, also at six channels. This announcement covers only the Structera X memory expansion line, not the Structera A near-memory compute controller that Marvell showed us last year. Still, CXL is focused on optimizing either bandwidth per core (since CXL bandwidth is in addition to native DDR bandwidth) and also capacity expansion.
PCIe Gen6 infrastructure and CXL 3.2 means we get roughly twice the bandwidth over the link, so that is how Marvell is adding more bandwidth from more memory channels.
Both new controllers stay on Marvell’s 5nm process and have LZ4 compression. Compression means the installed memory is storing more than the physical DRAM capacity. In this generation, Marvell is ensuring that the LZ4 can keep up with the interface so it is not a bottleneck. Here is the comparison table with key specs:
Structera X 3506 pairs six DDR5 channels with LZ4 compression at 250GB/s, while the 3406 runs DDR4 with six channels at 1600MT/s and 3DPC. That lets the DDR4 part take 18 DIMMs for up to 9TB per controller, and the DDR5 3506 takes 12 DIMMs for up to 6TB. CXL 3.2 lets up to four hosts share pooled memory, with up to 256GB/s of host bandwidth, double the prior generation’s 128GB/s.
We have known that memory pages have varying levels of compressibility, and Marvell gave us some data on that.
Final Words
We covered the first-generation Structera X and Structera A when we visited Marvell’s labs last year, including how line-rate LZ4 compression makes attached memory roughly half as costly per gigabyte. That hands-on look explains why CXL expanders are attractive as AI demand tightens DRAM supply and pushes DDR5 prices up.
For hyperscalers, this seems like a better version of the 2000 series. Unlike many of Marvell’s competitors who are moving to four channels in their CXL 3.x generation, six channels put 50% more DRAM behind a single controller.