Samsung Electronics (005930.KS) has deepened its alliance with U.S. artificial intelligence chip designer AMD, unveiling technology that expands memory capacity in AI servers. The strategy calls for memory makers and fabless chip designers to join Big Tech's AI data center projects at the design stage, broadening their memory and storage businesses at the same time.
Samsung said it jointly demonstrated a memory expansion solution based on Compute Express Link (CXL) with AMD at the OCP Global Summit 2026, which opened on Oct. 12 in San Jose, California. The OCP is a forum where global information technology, semiconductor and server companies discuss hardware design and standards for AI data centers.
Shim Ho-joon, vice president of the memory business at Samsung's Device Solutions division, outlined the company's AI memory strategy in a keynote presentation, built on three pillars: speed, memory expansion and data persistence.
Samsung plans to raise computing efficiency with eighth-generation high-bandwidth memory (HBM5), custom HBM, zHBM and processing-in-memory (PIM); address capacity limits with CXL; and improve the storage and management of large data volumes with next-generation solid-state drives and quadruple-level cell (QLC) NAND technology. Rather than simply supplying high-performance, high-efficiency memory, the company intends to offer a total solution that lifts the performance of entire AI infrastructure.
The event marked the first time the two companies have shown AI memory technology developed jointly since Chairman Jay Y. Lee met AMD Chief Executive Lisa Su in March.
The spread of AI agents that carry out tasks on their own has sharply increased the volume of data handled during inference. The KV cache, which temporarily stores past conversations and information for reuse, has grown larger, making capacity as important as speed for AI memory. Even fast central processing units and graphics processing units cannot deliver full performance when memory runs short.
The two companies built the technology on CXL, which links CPUs and memory at high speed to overcome capacity limits. Samsung presented memory pooling, a technique for managing CMM-D (CXL memory module DRAM) that allows multiple systems to share memory according to workload. The approach lets operators respond to shifts in demand without overprovisioning memory in every server, cutting data center investment and operating costs.
Samsung also organized its exhibition space around the AI computing and inference stages. The tokenization solution zone displayed HBM4E and HBM5, custom HBM concept products and LPDDR5X-PIM, a low-power double data rate memory with processing-in-memory. The company showed 2-nanometer gate-all-around wafers alongside Groq's language processing unit wafers and Nvidia's Grok 3 LPX system, highlighting its work with global AI companies. In a demonstration of an edge AI accelerator using LPDDR5X-PIM, it also showed technology that performs some computation inside the memory itself to reduce data movement and power consumption.
The KV cache solution zone featured CXL memory, enterprise SSDs, vector databases and direct storage, technologies that optimize how AI inference data is stored and moved. The aim is to design systems that manage data efficiently rather than merely compute it quickly. Samsung emphasized its co-design capability, which extends beyond chip manufacturing into design, software and performance validation.
SK hynix (000660.KS) joined the technology contest at the same event, where Kim Ho-sik, vice president in charge of memory systems research, unveiled a memory-centric AI rack system. That system also uses CXL, sharply raising data transfer speeds for workloads that require high-performance computing.
