Fault-tolerant quantum computing developer Alice & Bob has published a summary of technical milestones from Phase 1 of PROQCIMA, the French government’s 10-year, €500 million ($561 million USD) quantum procurement framework managed by the Defense Innovation Agency (AID) and the Direction générale de l’Armement (DGA).
Following a May 2026 national quantum strategy update, the French government officially accelerated PROQCIMA’s target roadmap from 128 logical qubits to 1,000 logical qubits by 2032, doubling the program’s annual budget. Stage 1 (2024–2028) allocated €60 million ($67.3 million USD) across the Phase 1 “examination” period for the five competing French hardware candidates (Alice & Bob, Pasqal, Quandela, Quobly, and C12), and is transitioning into Phase 2 (2026–2028)—a €150 million ($168.3 million USD) competitive phase (€30 million ($33.66 million USD) per company) that will narrow the cohort to three selected finalists before choosing the top two industrialization winners after 2030 (targeting 2,048 logical qubits).
| [ Alice & Bob PROQCIMA Phase 1 Hardware Milestones ] | ||
|---|---|---|
| Demonstrator Pillar | Hardware Configuration | Demonstrated Technical Capability |
| • Physical Demonstrators | • Three QPUs (Two 6-qubit chips, One 12-qubit chip) | • Assembled, calibrated, and operated for error-correction validation. |
| • Noise-Biased Logic | • Noise-Biased CNOT Gates | • Executed gates between cat qubits while preserving built-in bit-flip protection. |
| • Syndrome Extraction | • Measure-and-Reset Auxiliary Sequences | • Executed auxiliary qubit syndrome readouts and resets for QEC cycles. |
| • QEC Repetition Code | • Distance-3 Repetition Code (3 Data Qubits) | • Ran multiple error-correction cycles; full-register logical error rates measured (not yet below threshold). |
| • Non-Clifford Operations | • Single-Qubit Non-Clifford Gate | • Implemented non-Clifford gate on a cat qubit, establishing a baseline for fault-tolerant magic state injection. |
| • Automation & Control | • Proprietary MnR (Monitoring & Recalibration) Software | • Tracks 50+ performance indicators per qubit to automatically correct drift during QPU idle times. |
To satisfy Phase 1 feasibility requirements, Alice & Bob operated three independent hardware demonstrators—two 6-qubit superconducting chips and one 12-qubit chip—evaluating the building blocks of its bosonic cat-qubit error-correction architecture. The company also constructed a digital twin of its processor using experimental telemetry data to establish the coherence and fidelity parameters required to operate below the fault-tolerant error threshold.
Review the announcement on Alice & Bob Newsroom here and examine the national framework guidelines on the French National Quantum Strategy Portal here.
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