SpacemiT did not launch its V100 server processor on its own. At the RISC-V China Summit in Shenzhen on October 19, the company and the XiangShan open-source processor team also introduced three complete servers built around the chip, along with accelerator validation and operating system support aimed at getting RISC-V machines into data centers.
The three systems are the C2201 compute server, the G5201 AI server and the S5236 storage server, covering general-purpose computing, AI acceleration and large-scale data storage. The G5201 holds eight full-height, full-length, double-width accelerator cards and supports high-speed RDMA cluster networking. SpacemiT says it has been validated with domestic accelerators including Kunlunxin's M100. The company is also offering server motherboards, firmware, BMC management and hardware reference designs so partners can build their own branded machines without starting board design from scratch.
Software is the other focus. SpacemiT says V100 implements five RISC-V server specifications in silicon, firmware and the operating system: RVA23, Server SoC, Server Platform, Boot and Runtime Services (BRS) and the security model. It reports passing all BRS tests. As a result, openEuler, openRuyi, openKylin, Debian, Ubuntu, Fedora, Red Hat and Rocky Linux can be installed, booted and run directly. Embedded RISC-V chips have typically needed a custom operating system build for each part.
For multi-tenant clouds, V100 supports the RISC-V H extension, AIA and an IOMMU for hardware virtualization of CPU, memory, interrupts and I/O. SpacemiT says these virtualization extensions already have native upstream Linux support, so no custom kernel is needed. The chip also includes a hardware root of trust, a native RISC-V trusted execution environment and RERI RAS support. The company is pitching lightweight micro-VMs on V100 as a way to isolate cloud AI agent workloads at close to container-level overhead.
The chip itself uses a 46-core hybrid design with six XiangShan Kunminghu V2R2 cores and 40 SpacemiT X100 cores, running at up to 2.4GHz. Two chips can be linked coherently for up to 92 cores. Each chip supports eight DDR5 channels and 52 PCIe 5.0 lanes. XiangShan is led by the Institute of Computing Technology of the Chinese Academy of Sciences.
SpacemiT calls V100 the first general-purpose chip fully compliant with the RISC-V server specifications. Founder and CEO Chen Zhijian said the chip marks the company's move from devices to the cloud.
The specifications and compliance claims come from SpacemiT.
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