Key takeaways ▼
Chips&Media has announced a data compression technology aimed at one of the constraints in artificial intelligence hardware: moving data fast enough to keep processors busy. The South Korean semiconductor intellectual property supplier says its new Feature Map Compression IP marks an expansion beyond video applications into the broader multimedia and AI infrastructure markets.
Announced on October 6, the technology targets the activation values, or feature maps, generated as neural networks process information. These intermediate results can create substantial traffic between an AI processor and external memory. When memory cannot deliver data quickly enough, even a powerful neural processing unit, or NPU, can spend time waiting instead of computing.
Chips&Media’s approach is to compress that data as it moves through the system, then reconstruct it exactly when needed. The company says its core compression algorithm and C-model are ready, with hardware implementation scheduled for completion in the first quarter of 2027. The announcement therefore introduces a development program with reported algorithm-level results, rather than a completed hardware implementation.
According to Chips&Media, testing across vision networks including ResNet, MobileNet and YOLO produced bandwidth reductions of 35.2% for FP16 data, 45.7% for BF16 and 53.5% for INT8. These formats represent different ways of storing numerical values used in AI workloads. The reported savings suggest an opportunity to reduce memory traffic, although they should not be interpreted as equivalent percentage gains in application performance.
The compression is lossless, meaning decompression restores the original data without alteration. That distinction matters for chip designers seeking efficiency improvements without changing the numerical information supplied to their models. Unlike approaches that sacrifice data precision, this method is intended to preserve the values used during inference. Actual system benefits will still depend on the workload and implementation.
Integration is another part of the pitch. Chips&Media describes the design as a lightweight inline AXI bridge positioned between an existing NPU and the AXI bus. It says the architecture requires no internal SRAM and reuses the AXI clock, aiming to limit hardware area and simplify adoption. Support covers INT8, FP16 and BF16, with processing designed to keep pace with high-speed data flows.
Why it matters
The announcement addresses a practical problem in AI chip design: adding computing power does not automatically make a system faster. If a processor is constrained by memory bandwidth, additional arithmetic capacity can remain underused. Reducing the volume of data transferred could help existing compute resources do more useful work, provided compression and decompression do not introduce offsetting delays.
Power consumption makes the same issue relevant to edge devices. Memory traffic contributes to energy use, and mobile or embedded products operate within tight power and thermal budgets. If the proposed IP delivers its intended benefits in silicon, designers could gain greater flexibility when balancing throughput, battery life and heat. The release, however, provides no measured system-level power savings or completed-hardware performance results.
For Chips&Media, the move also broadens its commercial opportunity. The company’s established business centers on video codec IP licensed to semiconductor designers. Feature map compression extends that expertise into AI data movement, potentially giving customers another component to incorporate into their chips. Its commercial impact will depend on successful implementation, customer evaluation and eventual adoption.
The roadmap reaches beyond vision inference. Chips&Media says it plans to explore static weight compression and compression of the key-value, or KV, cache used by large language and vision-language models. Those are future directions shaped by customer requirements and workload characteristics; they are not capabilities demonstrated by this announcement.
Bottom line: The next milestone is hardware completion in Q1 2027. What matters thereafter will be evidence of achievable bandwidth savings, latency, power consumption and integration costs under representative workloads. Chips&Media has identified a meaningful bottleneck and reported promising compression results. Turning those results into dependable hardware will determine whether this expansion produces a useful building block for future AI systems.
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WAVE-P: Hardware Acceleration for the APV Professional Video Codec
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