When I started my career in semiconductor engineering over 30 years ago, the playbook was simple. The industry focussed on building general-purpose processors, shrinking transistors every couple of years to keep pace with Moore’s Law and leaving software developers to figure out how to leverage the extra speed.
Today, that playbook is obsolete. The physical limits of atomic miniaturisation have been reached, meaning that simply shrinking transistors is no longer enough to deliver the performance leaps the market demands. Instead of forcing software to adapt to generic silicon, engineers are now tuning physical hardware to run precise algorithms, marking an official entry into the era of domain-specific architectures.
The silicon specialisation imperative
The transition towards domain-specific architectures is driven by a simple reality: every major technology player now wants to own its silicon destiny. Whether it is leading AI companies, hyperscalers or major cloud providers, these companies are no longer satisfied with off-the-shelf, one-size-fits-all processors. They want custom chips designed specifically to protect and run their unique intellectual property. These companies are no longer waiting on mass-market suppliers, they are building their own silicon in-house, bypassing supply chain dependencies, lowering their total cost of ownership and reducing overdependence on any single hardware giant. Custom chips have become a supply chain strategy, not just a performance one. An ASIC tailored for a precise workload can run complex matrix math almost instantly at a fraction of the energy a general-purpose processor would consume. The numbers bear this out, with AI processing revenue exceeding $200 billion in 2025, nearly a third of all global semiconductor sales, according to Gartner.
To support the massive data pipelines required by modern AI, the industry has shifted towards High Bandwidth Memory (HBM), where memory companies release new architectures every 12 to 18 months. Power and cooling have become equally critical bottlenecks. While cooling once relied on simple metal heat sinks, today the focus has shifted to liquid and water-based systems to manage thermal limits in data centres. The market is also moving away from monolithic silicon toward modular chiplet designs, placing multiple smaller dies in a single package using advanced 2.5D and 3D packaging. This also enables 3D stacking, which layers logic and memory vertically to reduce signal travel distance. If one part of the system needs an upgrade, engineers only redesign that specific die, not the entire chip, significantly accelerating time-to-market.
AI is now designing the designers' work
AI is not just driving the demand for custom silicon, it is also starting to change how we design the chips themselves. Early in my career, it was common to see teams of 200 to 300 engineers dedicated to designing and verifying a single complex chip. Today, electronic design automation (EDA) tool vendors are building AI into their workflows to automate repetitive tasks, analyse log files and speed up verification.
My take on this is pragmatic. In the software world, people predicted that AI would deliver immediate 80% productivity gains, but the reality on the ground is closer to 15% or 20%. Chip design will likely follow a similar, gradual path. AI will make engineering teams more efficient, but it will not replace deep human expertise. If anything, the engineers who will thrive are those who learn to work alongside these tools, not those who wait for the tools to do the thinking.
The true challenge is complexity and the acute shortage of talent capable of handling it. India alone accounts for nearly 20% of the world's semiconductor chip design workforce, yet the pipeline of engineers trained for this level of complexity remains thin. Hyperscalers have the capital, what they lack is the talent. As designs push down to advanced technology nodes like 2-nanometer and 18-angstrom, we encounter physical phenomena that simply did not matter at older nodes. Obstacles like leakage currents, thermal management at scale and intricate power distribution require highly specialised skills.
New paths forward: RISC-V, Cloud Electronic Design Automation (EDA), and industrial IoT
Some relief is coming from the cloud, where EDA tools are becoming available on a pay-as-you-use model, making design infrastructure more accessible. We are also seeing the rise of open-standard CPU architectures like RISC-V, which is gaining serious traction for industrial and mid-market chips because it eliminates the heavy licensing fees tied to Advanced RISC Machines (ARM) and as ARM moves deeper into SoC development and closer to hyperscalers, some chip manufacturers are finding themselves competing with their own architecture provider. Just as a modern vehicle from a premium automobile manufacturer now contains 60 to 70 chips, factories and automated manufacturing lines will soon require millions of specialised, cost-effective processors. The domestic momentum is undeniable, with India’s semiconductor market valued at $52 billion in 2024-25 and projected to reach $103.4 billion by 2030, growing at a 13% CAGR.
Open architectures and cloud tools lower the entry barrier, but the real challenge is navigating the full chip lifecycle, from architecture and design through to testing and validation. From what I observe across the industry, very few organisations can manage this entire pipeline without stitching together multiple partners, a fragmentation that introduces significant hidden costs and execution risks. This gap is especially pronounced in automotive and industrial IoT, where analogue and mixed-signal engineering must integrate seamlessly with digital design and finding teams that can do both remains a genuine constraint.
The future of technology belongs to those who own their silicon. The path is complex, but the companies that get this right will not just gain a competitive edge, they will own the foundation that everything else is built on.
(The author is Senior Vice President, VLSI BU, Tessolve. Views are personal.)