Micron’s memory boom: Is the cyclicality really ending?

In Breaking Analysis 322, we shared with you that our forecast of a $1 trillion silicon business arrived two years earlier than we had forecast.

The reason for our 24-month miss was the bottleneck had moved from graphics processing units to memory. Micron Inc. gave us a new datapoint in its third-quarter earnings print. It said DRAM prices rose by more than 60% sequentially in the quarter, while the number of bits shipped barely grew. Today we address what that means. Here’s the key question we ask today:

Is this undersupply temporary or is there a structural change in the economics of memory?

We believe both forces are at work. This week we participated in a webcast with Micron President and Chief Technology and Products Officer Scott DeBoer. The roadmap he showed us underscores the importance of memory with respect to artificial intelligence performance. New customer take-or-pay agreements Micron has introduced a change how risk is shared.

At the same time, customers are being forced to adapt to higher costs. Qualitate’s proprietary research gives us a window into those customer decisions. Our investigation tries to determine whether these changes can make memory less cyclical, and what evidence would tell us that the familiar cycle is returning.

In this Breaking Analysis, we share how AI is changing the economics of memory. We reason through the implications of the massive divergence between memory average selling prices and bit growth, we discuss the strategic role of high-bandwidth memory and the changing memory storage hierarchy in the context of Micron’s roadmap. We’ll then bring in data from Qualitate and go deep within the supply chain. Specifically, we’ll dig into how fabless designers, IDMs, hyperscaler custom-silicon teams and design-verification engineers are dealing with HBM and Chips-on-Wafer-on-Substrate or CoWoS supply constraints. We’ll also share how memory price increases are affecting the buying patterns of end customers.

Finally we’ll close with some keys to watch as to whether memory cyclicality will return or if there’s a permanent change in the cycle dynamics because of AI.

Access the full slide deck here with bonus data in the appendix.

How AI is changing memory economics

The working premise we’re testing is that a structural change and a strong memory cycle can coexist.

Memory increasingly determines whether an AI system can keep its expensive processors utilized and productive. Delivering that memory consumes more manufacturing resources and requires closer engineering collaboration with design partners. Those changes mean that Micron, SK Hynix Inc. and Samsung Electronics Co. Ltd. are becoming significantly more strategic  suppliers.

But today’s price increases are a function of scarcity. High prices bring more investment but also give customers a stronger reason to defer spending, redesign architectures or consume infrastructure differently. The key is trying to understand the difference between ongoing strategic importance and the magnitude of the current scarcity price premium. We believe Micron can become more differentiated but over time it will still be exposed to cycles. The unanswered question is how much pricing power and profitability endure as supply loosens and and customers adapt.

The divergence in ASPs and bit volumes breaks the normal memory pattern

As Dr. Robert Castellano describes in his newsletter, the divergence between memory ASPs and bit volume growth is a new and defining characteristic of today’s semiconductor market. Historically, these two metrics moved in the same direction and a collapse or surge in pricing typically reflected a proportional shift in overall unit demand.

Today, a significant gap between high ASPs and flattish bit shipments exposes structural, supply-side tightening and an aggressive shift toward specialized AI hardware rather than an organic, broad-based demand explosion.

This was our starting observation which showed up in Micron’s own earnings deck. In fiscal Q3, DRAM average selling prices increased sequentially in the low-60s percentage range, while bit shipments increased only in the low single digits. As a result, DRAM revenue rose 67%.

Micron’s most recent Q4 print gives us new data. Specifically, price growth moderated to the high teens, but prices continued to rise, and bit growth remained in the mid-single digits. This speaks to a continued strong price environment, not equivalent growth in the physical amount of memory shipped. Remember, too, that the ASP reflects a blended rate. So product mix is a key determinant of revenue and margin.

Low shipment growth does not mean weak demand when supply is constrained like it is today. The obvious conclusion is that supply constraints are producing a large near-term revenue boost. The question is how much of that benefit continues when production expands and customers adapt to the changing economics of AI. That is what the roadmap, contracts and customer data help us assess.

It’s not just about HBM

There’s a tendency to put everything into an HBM story. In Q4, Micron’s Cloud Memory business reported a lofty 83% gross margin, flat with the prior quarter. Management said higher pricing helped, but a higher mix of HBM offset that benefit. Micron doesn’t disclose HBM standalone margins, but the shift in manufacturing capacity toward HBM underscores the dynamic we discussed earlier between ASPs and bit growth.

Specifically, Micron tells us that HBM3E requires roughly three times the wafer supply to produce the same number of bits as DDR5 at the same technology node, with more complex packaging. As well, the HBM prices in Q4 were negotiated in 2025, whereas DRAM pricing was more exposed to spot pricing dynamics. So these factors put pressure on what are elevated margins.

Micron expects higher HBM pricing in calendar 2027 to narrow its margin gap with conventional DRAM. But the long-term test is whether Micron earns attractive returns through product transitions and weaker pricing conditions, rather than whether one product has the highest margin during a shortage.

Memory capacity and bandwidth serve different needs

Scott DeBoer laid out his view of the expanding data center memory hierarchy with standard, custom and vertical HBM at the top (near memory), followed by high capacity and lower power DRAM (main memory), then SSDs and AI-class NAND (context memory)  and high capacity SSDs for databases and data lakes.

A key point is that AI performance depends on where information lives and how quickly it can reach the processor. Capacity is the amount of data that fits in the package. Bandwidth is the amount of data that moves each second. HBM is key because it gives the GPU a fast local working space.

Server memory provides additional capacity, while flash storage holds data and selected cached context at lower cost. During inference, the system saves intermediate calculations in the KV cache so it can reuse work as it generates an answer. Longer conversations and more concurrent users can expand that working data set and can flush the KV cache; so storage suppliers like VAST, Dell and others create a virtual space with lower cost SSDs so that the KV cache doesn’t have to endure a refresh.

Ultimately, the buyer’s objective is a balanced system that meets a specific workload’s latency, throughput and reliability needs. Buying more memory can help when memory is the constraint. It does not always improve every workload. The right viewpoint is cost per useful task at the required service level, including the effect on GPU utilization, energy and the number of systems needed.

How HBM sucks up more manufacturing capacity and what that means

There are always opportunity costs when producing particular types of memory. At the KeyBanc investor conference, Micron’s Sumit Sadana described a three-to-one ratio between HBM3E and conventional DDR.

In other words, capacity that could produce roughly three units of DDR bits instead produces one unit of HBM bits. He said that moves closer to four-to-one by HBM4E. The reason for this is that very high bandwidth requires more connections, more silicon resources and more complex packaging.

We believe this is the clearest example of the tradeoffs facing memory makers between the technical roadmap and conventional memory pricing. Specifically, more AI memory can absorb resources that would otherwise support other DRAM products, so investment does not translate directly into proportional growth in saleable bits. But the dynamic works in both directions. If HBM demand weakens, reallocating capacity could release more conventional DRAM supply over time. Of course it’s not that simple. There’s qualification, equipment and learning curve constraints that require time.

How Micron prioritizes investments in its roadmap

The company is pulling two levers at once. It is making memory more specialized and closely integrated with the customer’s processor, while at the same time increasing the number of bits manufactured in a given area. HBM4 is already in high-volume manufacturing.

HBM4E and later memory placed directly on the processor are roadmap items, with target dates. On the manufacturing side, Micron is looking to get a mid-twenties percentage improvement in DRAM bit density with its next generation, called one-delta, ramping in the second half of 2027. Its G11 flash roadmap targets approximately twice the density of G9. That is for NAND development; it does not affect HBM capacity.

We believe these gains are an essential element in the context of scarcity. Meaning better density and yields will improve Micron’s economics. Their ultimate impact depends on learning curve and other dynamics – e.g. ramp speed, the product mix, Micron’s capital investments and of course end customer demand. The roadmap we heard from DeBoer emphasizes the continuing importance of memory but no one can guarantee that peak pricing is a permanent condition.

Qualitate data shows how chip designers are dealing with supply challenges

Qualitate’s silicon design and sourcing panel gives us a fresh view of the supply problem. Eight of twenty-two respondents in the survey said memory or HBM was their largest current constraint. Seven said the main constraint was advanced packaging.

Remember, these are small N, deep dive interviews and the responses support the view that constraints extend beyond a single chip or an announced wafer capacity data point. The implication for our premise is that new fabrication capacity alone may not resolve every constraint. Qualification, packaging and system integration still determine how quickly useful hardware reaches customers.

Qualitate data tells us that chip designers across hyperscalers, integrated device manufacturers (IDMs), and fabless firms are responding to acute High Bandwidth Memory (HBM) and advanced packaging shortages by fundamentally replacing the traditional “design-then-source” workflow with a supply-aware co-design methodology. Because physical availability has become the key constraint on shipping finished silicon, engineering teams are employing specific architectural, packaging, and procurement strategies to mitigate these bottlenecks.

These include:

• Architectural adaptations and design compromises such as trading peak performance for supply;
• Downsizing HBM configurations;
• Leaning more heavily on larger SRAM designs;
• Moving away from silicon interposer constraints to reduce reliance on TSMC CoWos packaging;
• Standardizing on open chiplet interfaces like UCIe;
• Building specialized ASICs;
• Dozens of other innovative strategies to reduce their supply constraints.

In a moment, we’ll turn to a separate Qualitate data set that describes what enterprise practitioners are doing about higher infrastructure costs.  But first let’s look how memory is affecting the infrastructure bill of materials (BoM).

Memory is becoming a much larger portion of the AI infra BoM

To do this we need a way to discuss the customer’s bill. Below we take a hypothetical scenario to model how memory is affecting overall infrastructure costs.

The percentage of memory costs for AI infrastructure will vary by customer and the nuances of the rack configuration. But we can use rules-of-thumb and a sensitivity analysis to understand how price increases affect the portion of the BoM that is memory.

Assume for a moment an unchanged system configuration, unchanged non-memory costs and a sixty percent increase in the purchase price of its memory:

• If memory began at twenty percent of the bill of materials, total cost rises twelve percent (12%);
• At thirty-five percent, total cost rises twenty-one percent (21%);
• At fifty percent, total cost rises thirty percent (30%).

The higher the starting memory content, the greater the exposure. The actual customer response can include less memory, a different system or greater utilization. Our point is that memory can materially change the business case even when the rest of the system stays the same.

How enterprise customers are addressing the memory price challenge

Let’s come back to a different Qualitate data set from the enterprise customer perspective to better understand how practitioners are dealing with the challenge of higher memory prices.

According to the Qualitate data, memory and CPU cost inflation is being felt across the entire infrastructure estate. Enterprises are responding through a consistent set of coping strategies, none of which involve simply absorbing the cost.

One healthcare practitioner sums up the changing price and tech inflation dynamic saying: To get the same number of GPUs this year as opposed to 2 years ago, to get the same GPU capacity is what, 3–4x the cost? That’s pretty insane when you’re used to following Moore’s Law.

One practitioner describes trying to push purchases out saying it is not a no, but it is a not now push. A security-focused organization says higher hardware costs shift the equation toward cloud consumption.

The following table shows how end customers are dealing with these pricing challenges:

Source: Qualitate, 2026

We will watch whether these responses reduce deployment, improve utilization or simply move the demand elsewhere.

Customers are getting smarter about model routing and capacity utilization

One practitioner says the organization has reduced usage of some large frontier models where smaller or open-weight alternatives passed its benchmarks. Another questions keeping premium dedicated GPUs available around the clock for variable demand. Quantization, batching and smaller models are among the strategies the customers point to. Their effectiveness depends on the application, and we don’t know exactly how memory was impacted but these operational moves are direct responses to memory price increases.

Our interpretation is that expensive memory raises the value of doing less unnecessary work and keeping expensive resources productive. That can lower memory or compute needed per task. At the same time, lower task costs can often catalyze more usage. The best indicator to watch is useful-task cost at an SLA, together with utilization and aggregate deployed capacity. Scarcity pricing increases the demand for efficiency and techniques or products that emphasize efficiency are increasingly attractive in the current environment.

Customers are changing suppliers when they can get capacity

Let’s look at a third set of responses to test platform and supplier choices.

One practitioner chose AMD because it gave the ability to fit more of the model on one card. That is directly relevant to our thesis in that a customer can value more memory per accelerator because it may reduce the number of accelerators or the communication needed for a workload.

Separately, a practitioner describes choosing a supplier that could deliver comparable equipment. That is evidence of availability affecting a selection. Today, any credible supply will get scooped up. The point is, taken together, these examples show how memory fit and delivery availability influence supplier choices. The practical indicators practitioners should consider are delivered performance, software effort, interconnect requirements, time to production and total cost per useful task. These are the measures that will validate or challenge Micron and other AI vendors’ pricing power over time.

The outcome and its cost determine customer value

Putting the customer angle at the center of our conclusion is important. Suppliers are reporting strong demand while individual practitioners describe strategies around deferral and redesign. Those two dynamics can coexist because customers, workloads and budgets differ. Dell’s quarterly filing reports substantial inflation in memory components and its pricing response. HPE management, when asked about passing through higher memory prices, had no hesitation in referring to its customer discussions about higher prices.

These are the themes we’re hearing from vendors. Qualitate gives us examples of buyers making selective tradeoffs. We believe the best measure is cost per useful task or outcome at the required quality and latency. More memory can increase the hardware bill but lower task cost if it avoids extra GPUs or keeps them productive. Conversely, an expensive system with low utilization can undermine the business case. The indicator is whether customer ROI supports continued deployment after the price premium hits the final bill.

How Micron is using strategic supplier agreements (SCA)

Let’s look at how Micron is capitalizing on the current demand picture. The most obvious business-model change is the strategic customer agreement.

By the Q4 report, Micron had signed 26 SCAs, which are committed volume and/or take or pay contracts. Micron estimates these agreements cover more than 35% of its revenue through 2030. These are multiyear supply arrangements, generally with binding purchase volumes. Three-quarters of the expected revenue under these agreements has a defined pricing framework, and a majority of that portion uses price bands. Customers receive supply assurance and, in many cases, a ceiling on prices. Micron receives volume commitments, often a floor on prices, and more confidence to plan capacity.

We believe this is substantive evidence that the industry’s economics are evolving. It does not remove risk. Micron’s own filing warns about enforcement disputes, customer inventory and oversupply when final demand falls short. Our test will be what these agreements actually protect through the next weaker market.

Does this end the cyclicality in memory?

Let’s poke at the cyclical argument that everyone’s concerned about. In other words, will AI smooth out the brutal cycles that investors in Micron have endured for years.

The strongest argument is very high prices fund new capacity, better manufacturing yields and more efficient use of each bit. Micron’s own roadmap contains evidence of this response. Its fab program adds multiyear capacity. But customers can reduce specifications, delay purchases or move workloads. And if HBM demand weakens, suitable capacity can eventually return to conventional DRAM, increasing supply there and potentially creating conditions for returned cyclicality.

Micron explicitly warns about this mechanism in its risk factors from its latest 10K filing. Take or pay contracts can ease the pain, but they do not make final demand disappear as a key variable. A buyer that committed to more than it needs can accumulate inventory. We therefore have no choice but to leave the end of cyclicality as a somewhat open question. The meaningful milestone will be saleable supply at useful yields meeting productive demand over time.

The likelihood that at some point in the future, demand and supply will come into balance is reasonably high.

What to watch in the months and quarters ahead

First, watch ASPs together with bits. The bull case is attractive economics as physical volume and productive use expand. A price decline alone doesn’t signal a bust if it unlocks deployment. Second, watch margins after the current price surge. Product mix, new-fab costs and utilization will be important. Third, watch the supply ramps. A cleanroom or first wafer milestone does not tell us how much qualified memory customers can actually procure.

The question is whether saleable output from the fabs comes into a robust market or if it hits after demand has slowed. We believe these tests are more useful than just extrapolating the current margin or putting a precise date on a future glut. The evidence today is clear. Supply is scarce and the industry is ramping up to meet demand.

The other tests are closer to the customer. Do strategic agreements stay in place when the market weakens – it’s unlikely? Watch volumes, pricing protections and any disputes, renegotiations or force majeure situations like we saw with Oracle and Blue Owl. Do customers earn enough useful output to justify their memory bill? The Qualitate examples show how the configuration, model choice and ownership decision can change.

Finally, do orders turn into productive installations, or do commitments outrun consumption? Tight supply encourages customers to overstate forecasts or reserve more than they ultimately need, which Micron itself identifies as a risk. The bull case becomes stronger if contract performance, customer returns and actual deployment remain healthy as supply expands.

That is how we will distinguish a more durable business from an unusually strong phase of the cycle.

There’s no question that today the cycle has changed. The question is what will happen if and when the demand picture reverts.

The cycle has changed, for now…

Our conclusion is that memory’s economics are changing and AI has positively smoothed the cyclicality for the mid-term. But the data does not convince us that cyclicality has ended. The bull case/structural argument is that memory is central to useful AI performance, high-bandwidth products consume more manufacturing capacity, and Micron is building a more differentiated relationship with customers.

The bear case/cyclical argument is just as credible in our opinion. Specifically, an  extraordinary price environment invites supply, optimization and delayed purchases. Qualitate data shows the customer response already taking several forms. For suppliers like Micron, the test is the return they earn after scarcity eases. For customers, the test is productive work delivered at the required service level. We believe the best way to follow this story is to keep both sides on your radar. If volume, customer returns and contract performance improve as capacity arrives, the business may become less volatile. If inventories rise and demand fails to absorb supply, the familiar cycle will assert itself and the classical memory cycles will return.

What’s your call? Is the memory boom permanent and is the risk of oversupply under control by the memory makers? Or will the cycle re-emerge before the end of the decade?

Let us know what you think.

Here’s the full Breaking Analysis episode:

Disclaimer: All statements made regarding companies or securities are strictly beliefs, points of view and opinions held by SiliconANGLE Media, Enterprise Technology Research, other guests on theCUBE and guest writers. Such statements are not recommendations by these individuals to buy, sell or hold any security. The content presented does not constitute investment advice and should not be used as the basis for any investment decision. You and only you are responsible for your investment decisions.

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