CXMT expects to launch its first 4F² product, a server DDR5 RDIMM, by the end of the year, company president Cao Kanyu said in remarks reported by Yicai. The memory will be built on a denser cell layout, not yet commercialized, using vertical transistors to reduce the cell’s footprint by about one-third on paper. No speeds or capacities have been announced yet for the new product.
Cao spoke about the new RDIMM at the Integrated Chips and Chiplets Conference on Saturday. A 4F² cell is 2F by 2F at about two-thirds the area of current 6F² cells at the same feature size, and designs so far all stand the transistor up. The company has produced research and patent filings on the technology with papers in 2021, 2023, and 2025, and an 8Gb full-array research example was demonstrated at IEDM 2023.
Cao said CXMT’s version, the Vertical Surrounded Gate (VSG) transistor, has a channel that stands vertically with the gate wrapped around it, allowing stronger gate control with less leakage. Most importantly, standing the transistor up shrinks the cell. CXMT now has more than 300 published patent families tied to 4F², he added. The report says the industry as a whole is moving toward 4F² with 3D solutions that decouple DRAM and CMOS processes, combining them with wafer-level hybrid bonding, which allows logic and cell density to be optimized independently. Cao also covered CXMT’s own hybrid-bonding work, which began in 2019, with published patents.
Aside from this announcement, China’s primary DRAM maker has been in the news lately for its manufacturing and market-share gains. Its fifth-generation G5 DRAM technology platform, announced Sept. 20, is in mass production. TrendForce puts CXMT’s share of global DRAM revenue at 9.5% in the second quarter, up from 7.6% in the first, good for fourth place. Last November, CXMT showed off DDR5-8000 and LPDDR5X-10667. It has revealed itself as a manufacturer to be taken seriously by the biggest existing players.
Samsung showed off a 16Gb, 10nm-class 4F² DRAM design in its ISSCC 2026 paper in February. That one also used vertical-channel transistors (VCT), with the array bonded on top of the periphery using wafer-to-wafer hybrid copper bonding. The company claims the bonding raises dies per wafer by more than 20% with the same design rules. In April, The Elec reported that Samsung had a working 4F² VCT die on its sub-10nm “10a” process, with mass production targeted for 2028. Later South Korean reports clouded that date: the VCT version has since been split off as “D0a-V” with no timeline, and there is no firm timeline for adopting 4F².
SK hynix laid out plans at VLSI 2025 for a 4F² vertical-gate platform and 3D DRAM at nodes of 10nm and below, with circuitry bonded under the cell array. The April report also puts SK hynix’s 4F² debut at the 10b node, one step after Samsung’s 10a. Micron’s plans remain less clear, with no widely reported 2026 statement.
The announcement is perhaps more interesting for what wasn’t mentioned: capacity, speed, die density, process node, named customers, or intended volume. All we have is a date and a purported cell design, admittedly well-supported by the literature, but no product that has been tested by anyone outside of CXMT. Beyond Cao’s talk, CXMT hasn’t posted a release about the product in its Chinese or English newsrooms.
South Korean reports have said that CXMT’s initial products may only partly use 4F² and that producing stable units at volume is a separate challenge. With about 11 weeks left in the year, it will be interesting to see what CXMT actually delivers.