Export controls have kept ASML's most advanced EUV lithography machines out of China. Instead, the country's chipmaking industry has relied on less-capable deep ultraviolet (DUV) lithography machines. By using multiple exposures on critical chip layers, these older machines are still capable of producing performant silicon. However, as multiple patterns are applied there are more chances for defects, longer manufacturing times, and higher bills. We spoke to experts like Chris Mack, co-founder and CTO of semiconductor firm Fractilia, to find out how much further DUV can go.
For years, extreme ultraviolet (EUV) lithography has been seen as China’s biggest choke point in the country’s attempts to build cutting-edge chips. The machines, made exclusively by Dutch manufacturer ASML, use 13.5nm-wavelength light to print some of the most intricate features found on modern processors. Sales of ASML’s EUV systems are subject to export restrictions, forcing Chinese manufacturers to squeeze ever more out of older deep ultraviolet, or DUV, lithography instead. The EUV gap alone between China and the West is at least half a decade, according to some analysts.
But even without access to EUV machines, China has gotten surprisingly far in recreating what it offers through existing technology.
Teardowns of Huawei’s Mate 60 Pro in 2023 found the phone’s Kirin 9000S processor had been made by SMIC using a second-generation 7nm-class manufacturing process without EUV. More recently, analysis of Huawei’s Kirin 9030 found SMIC had pushed its DUV-based process closer still to the density associated with 5nm manufacturing – although it continued to lag behind the leading processes used by TSMC and Samsung.
Multiple patterning
The trick is multiple patterning. Rather than trying to print an overly intricate chip layer in a single pass, Chinese manufacturers are dividing up the complex design into several simpler patterns. Repeat the process enough times and you can etch up something approximating the proper layer you intended.
The trick works. But according to lithography expert Chris Mack, co-founder and CTO of Fractilia, asking whether a chip can be made without EUV overlooks the trade-offs manufacturers make in order to do it.
“When this transition first began, what everyone in the industry said as conventional wisdom is that cost-wise, three exposures on a 193 immersion tool cost about the same as one exposure on an EUV tool,” Mack said in an interview with Tom’s Hardware Premium. “At three, it was about even,” Mack explained. “But as soon as you hit four masks – 193 masks being replaced by one EUV mask – then EUV became more cost-effective.”
It’s also likely to produce a higher quality product with fewer defects. Each time a wafer is patterned, that new pattern has to line up perfectly with everything that’s already been etched beneath it. The more individual exposures needed to produce a single layer, the more opportunities there are for things to go wrong. “If you have, say, four 193 masks, you've got all those different overlays, and you've got all these different process variations that start to accumulate,” Mack said.
Chip designers can try and avoid that by leaving more space around features so the finished processor can actually be manufactured reliably. But that means the chip ends up bigger – and bigger chips become expensive very quickly. Making each die larger means fewer fit on every wafer, and wafers cost a lot of money – tens of thousands of dollars each.
“You don't sell wafers, you sell die,” Mack said. “The question is: how many die can I fit onto that wafer, and how many of those die yield, and therefore how many chips can I sell per wafer?”
The efficiency gap
There is some evidence of what that efficiency gap can look like in practice – albeit in memory rather than logic chips. In a June report, Morgan Stanley estimated that Chinese DRAM manufacturer CXMT was producing only around one-third as many bits per wafer as Western competitors. The analysts believed the older process node only accounted for around a third of that shortfall, but said access to lithography was a “hard ceiling” on Chinese memory development. “For advanced logic chips, in theory there could be other innovations to engineer around EUV, but they are not likely to be very efficient and effective,” said Douglas Fuller, a researcher at Copenhagen Business School, in comments to Tom’s Hardware Premium.
It is also why claims that China has reached a particular semiconductor process “node” need to be treated with caution. “If somebody says it's X node – the seven nanometer node, the five nanometer node, the three nanometer node – these words almost have no meaning,” Mack said.
That can be seen in SMIC’s latest chips. Reporting suggests its N+3 process represents meaningful progress towards 5nm-class manufacturing – but the actual measurements show it remains significantly less scaled than established 5nm processes from Samsung and TSMC. That doesn’t mean DUV has reached the end of its useful exploitation.
Stretching DUV's efficacy
Micron is an example of how far DUV can be stretched, producing competitive DRAM chips using DUV, multiple patterning and tight process control. Its 1-alpha generation of chips was developed without EUV. “They pushed 193 farther than any of the other memory makers did,” Mack said. “They were able to make very competitive chips with 100% 193 compared to Samsung and Hynix making them with many layers of EUV.”
Morgan Stanley believes CXMT’s planned move to 1-alpha DRAM – which it wants to use for HBM3e – is achievable without access to EUV, citing Micron as evidence. Indeed, “by the end of the decade, advanced packaging will allow firms to use DUV to produce the latest generations of DRAM,” reckons Fuller.
Micron also designed its products around the manufacturing technology available to it, rather than simply trying to recreate an EUV process on older equipment – something which could be a useful lesson for Chinese manufacturers. “If the entire ecosystem of 193 immersion were available to China,” Mack explained, “then they could probably push a long way with 193 multiple patterning, especially if they optimise designs for the fact that they're going to be using that.”
But Micron was making memory, whose highly repetitive structures make close co-ordination between chip design and manufacturing easier than it is for the much more complicated logic processors found in phones and computers.
“Memory is a lot easier than logic,” Mack said.
And even Micron eventually concluded that EUV was worth using. Its newer 1-gamma DRAM process uses EUV lithography, with Micron saying the technology helps it achieve more than 30% greater bit density per wafer than its preceding 1-beta generation.
EUV is hardly a magic wand, either. Mack points to stochastic effects – tiny random variations caused by the small number of photons involved in an exposure – which mean manufacturers can improve pattern control by increasing the EUV exposure dose. But it also pushes the cost back up quickly.
Because of that, Mack believes there is ultimately a limit to how far multiple patterning can economically substitute for EUV. “I would be hard pressed to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV,” he said.
That doesn’t mean Chinese chipmakers simply hit a technological wall and stop. They can keep pushing DUV while accepting larger dies, poorer yields, longer manufacturing times – or some combination of all three.
They can also throw capacity and money at part of the problem. Morgan Stanley assumes CXMT remains stuck on its 1-alpha process without EUV, yet still increases its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 simply by building more greenfield capacity. The bank also expects China’s AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030 through new advanced-node capacity, improving yields and heavy state support – while EUV, HBM and advanced software leave a persistent gap. And so without EUV, the experts reckon China can only get partway to bridging the gap with the West. ““I would be hard pressed,” said Mack, “to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV.”