Key takeaways ▼
Last year I wrote about Arteris’ introduction of multi-die support for coherent NoCs. This is a very big deal because hyperscalers and OEMs are now building large systems that depend on multi-chiplet architectures and require efficient traffic management between chiplets, in one case as many as 12 compute, fabric/cache and IO chiplets, plus HBM.
Beyond physical connectivity between chiplets, multi-chiplet systems demand effective traffic management, including bandwidth, latency, and quality of service (QoS) across multiple traffic streams. The Arteris Ncore Multi-Die solution addresses this need for coherent traffic across chiplets, yet similar support for non-coherent traffic is an even more common requirement. This is now addressed by the Arteris FlexGen Multi-Die solution.
Why traffic management is important between chiplets
Even within a single chiplet, traffic management is an important consideration. Today, the most common architecture to address this management is network on chip (NoC), widely preferred for scalability over traditional crossbar switch architectures, while still interfacing to all AMBA and other standard protocols.
This is all good within a chiplet, but what happens when you must send traffic between chiplets? One approach is to translate through a bridge to AXI and then go through a popular AXI to UCIe translator to hook up to a UCIe connector, with a similar arrangement mirrored on the other chiplet. This works fine, except that it doesn’t preserve traffic policy management, with inter-chiplet QoS carrying over to the next chiplet. This isn’t very architect friendly; traffic management needs don’t disappear at the edge of a chiplet.
A designer could of course handle this themselves by extracting all the QoS management information from the NoC on one side, adding it to the AXI data as sideband signals and reconstructing back into the NoC on the other side. Or they could use FlexGen Multi-Die, which does all this automatically by tunneling the NoC protocol through the UCIe link. This in effect makes the chiplet-to-chiplet interface transparent.
This flexibility allows architects and designers to concentrate on total system design and optimization. With FlexGen Multi-Die, the architect can start with a monolithic system design without needing to commit to what logic is going to go on what chiplet. They can experiment with partitioning options to see how chiplet-to-chiplet controller links at those boundaries will impact QoS, rather than hardwiring a partitioning at the outset.
Digging down a little more
Rick Bye, Director of Product Management and Marketing at Arteris, tells me that this solution is is very configurable and pretty agnostic to the PHY IP a designer will use. They are already working with several companies who have their own PHY IP, most notably AMD who have provided an enthusiastic endorsement for the Arteris solution. Over time, Arteris also expects to qualify this new capability with some of the commercial UCIe IP options.
Another very interesting feature of the Arteris Multi-Die FlexGen IP is that it can enable more efficient use of UCIe IP. Consider two chiplets A and B communicating. If all initiator traffic comes from A and all target traffic comes from B, then perhaps all that traffic can be piped through one UCIe IP on each side. If both A and B can initiate and be targets (not an uncommon scenario when replicating chiplets each containing an XPU and memory), FlexGen Multi-Die has no problem managing that traffic, up to bandwidth limitations.
However, indications are that at least some AXI-to-UCI bridges require two UCIe ports on each chiplet; one for initiation from A and one for initiation from B. In this case, FlexGen Multi-Die is more area efficient, more power efficient, and more I/O efficient. And of course more flexible for early partitioning experiments.
Very interesting. You can read more about Arteris HERE, and more about the Arteris Multi-Die solutions HERE.
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