SK Hynix Says Memory Hierarchy Must Be Optimized

Ahn Hyun, president of SK hynix, delivers a keynote speech at the 28th Semiconductor Exhibition(SEDEX 2026) held at COEX on October 14. Ahn Hyun, president and head of development at SK hynix, said in a keynote speech at ‘SEDEX 2026’ held on October 14 that the rapid expansion of the AI inference market is creating a new memory bottleneck. He stressed that, to address this, a strategy of optimizing the entire memory hierarchy is essential beyond simply improving the performance of individual products. The AI inference market is currently growing explosively as workload complexity, context length, and inference request volume multiply with one another. In particular, as demand rises for ‘KV cache’ capacity, through which AI reuses previous data, data movement between multiple layers from HBM to SSD is becoming more frequent. Ahn said that whereas past memory barriers occurred between processors and memory, the performance gap between different memory tiers and the movement itself have now become a new bottleneck. To resolve this bottleneck, SK hynix plans to further subdivide and diversify memory architecture. To narrow the performance gap between existing SRAM and HBM, the company is pursuing ‘3D Stacked DRAM’ technology, which directly stacks DRAM on top of logic semiconductors such as GPUs and NPUs. The structure is designed to dramatically reduce the physical distance between processors and data, improving performance while lowering energy consumption. The company also presented ‘HBF(High Bandwidth Flash)’ as a solution to capacity shortages. HBF is a next-generation memory technology that applies HBM stacking technology to NAND flash and is positioned between HBM and DRAM. Its target is to deliver about half the bandwidth of same-generation HBM while achieving roughly 10 times the capacity. Ahn explained that, given the read-intensive nature of AI inference, NAND-based HBF is optimal for improving system efficiency. HBM, the company’s flagship product, is set to evolve into ‘custom HBM’ optimized for each customer’s AI system. The plan is to mount a memory controller and customer-specific logic directly on the base die to provide an optimal architecture that goes beyond simple storage. Based on technological capabilities built from HBM1 through HBM4E, SK hynix plans to expand the memory ecosystem by combining CXL with next-generation storage technologies. Meanwhile, SK hynix set up its largest-ever booth at this exhibition and unveiled a broad range of its latest AI memory solutions. These included an HBM wafer bearing the signature of NVIDIA CEO Jensen Huang, 6th-generation 10-nanometer-class DRAM, and enterprise SSDs supporting liquid cooling. The company said it has finalized a strategy to drive sustained growth in the AI era by pursuing preemptive standardization of HBF and cooperating with global partners.