MemSilicon, a Chinese memory startup, says it completed tape-out of MountTai 2026, its first-generation high-density, high-capacity RRAM chip, on October 12. The company calls it the world's first high-density, large-capacity RRAM chip of its type, a claim that has not been independently verified. The chip has been taped out and is now going through validation.
MountTai 2026 is built on a 28nm CMOS process with a 1T4R cell structure. Capacity is 1Gb per chip, density reaches 30Mb per square millimeter, access latency is under 20 nanoseconds, and the chip integrates hardware error correction on die.
RRAM, or resistive random-access memory, stores data by switching a material between resistance states and keeps it when power is off. In the common 1T1R design, each resistive cell has its own selector transistor. As cells shrink, the area taken by those transistors and their wiring becomes a limit on density. The 1TnR approach lets one transistor serve several cells, cutting the transistor area per bit; MountTai 2026 uses one transistor for four cells.
Sharing a transistor brings problems of its own, including sneak current paths between cells, read and write disturbance, and reliability across operating conditions. MemSilicon says it addressed them at the circuit level with a negative-voltage design and unified reset scheme to suppress array leakage, multi-voltage-domain word-line drivers that separate high- and low-voltage read and write paths, adaptive protective bias to reduce mis-writes, and an adaptive tracking read circuit that works with the error correction to improve read yield at gigabit capacity.
The company's technology comes from the team of Liu Ming, an academician of the Chinese Academy of Sciences, which published research on a 28nm 1T2R RRAM design in 2020. Because the cells are built in back-end layers compatible with standard CMOS, the approach is meant for embedding non-volatile memory on logic chips.
MemSilicon is targeting on-chip storage for model weights, KV cache and parameters in SoCs, embodied AI devices and AI PCs, where SRAM is fast but large per bit and embedded flash grows harder to integrate as logic processes shrink.
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